Assignors: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) Filing date Publication date Application filed by Hewlett Packard Development Co LP filed Critical Hewlett Packard Development Co LP Priority to US11/049,306 priority Critical patent/US7373457B2/en Publication of US20050177688A1 publication Critical patent/US20050177688A1/en Application granted granted Critical Publication of US7373457B2 publication Critical patent/US7373457B2/en Assigned to HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP reassignment HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Original Assignee Hewlett Packard Development Co LP Priority date (The priority date is an assumption and is not a legal conclusion. Hewlett Packard Enterprise Development LP Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) Gaither Russ W Herrell Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Expired - Lifetime, expires Application number US11/049,306 Other versions US20050177688A1 Google Patents Cache coherence protocol for a multiple bus multiprocessor systemÄownload PDF Info Publication number US7373457B2 US7373457B2 US11/049,306 US4930605A US7373457B2 US 7373457 B2 US7373457 B2 US 7373457B2 US 4930605 A US4930605 A US 4930605A US 7373457 B2 US7373457 B2 US 7373457B2 Authority US United States Prior art keywords line gotl cache memory list Prior art date Legal status (The legal status is an assumption and is not a legal conclusion. Google Patents US7373457B2 - Cache coherence protocol for a multiple bus multiprocessor system US7373457B2 - Cache coherence protocol for a multiple bus multiprocessor system
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